SEGMENTATION IN 8086

Need of segmentation:

The need of memory segmentation is explained below:

1. The BIU (Bus Interfacing Unit) contains four special purpose registers called as segment registers. These are Code Segment (CS) register, Stack Segment (SS) register, Extra Segment (ES) register and Data Segment (DS) register.
2. All these are 16 bit registers.
3. The number of address lines in 8086 is 20. So the 8086 BIU will send out a 20 bit address in order to access one of the 1,048,576 or 1MB memory locations.
4. But it is interesting to note that the 8086 does not work the whole 1MB memory at any given time. However it works with only four 64 KB segments within the whole 1 MB memory.
5. The four segment registers actually contain the upper 16 bits of the starting addresses of the four memory segments of 64 KB each with which the 8086 is working at that instant of time.
6. A segment is a logical unit of memory that may be up to 64 kilo bytes long.
7. Each segment is made up of memory contiguous memory locations. It is independent, separately addressable unit.
8. Starting addresses will always be changing. They are not fixed.
9. Figure shows one of the possible ways to position the four 64 KB segments within the 1 MB memory space of 8086.

1. There is no restriction on the locations of these segments in the memory. These segments can be separate from each other or they can overlap.
2. In the users program there can be many segments but 8086 can deal with only four of them at any given time because it has only four segment registers.
3. Whenever the segment orientation is to be changed, the base addresses have to be changed and load the upper 16 bits into the corresponding segment registers.
4. Segment registers are very useful for large programming tasks that require isolation of program code from the data code or isolation of module data from the stack information etc.
5. Segmentation builds relocatable and re-entrant programs easily. In many cases the task of relocating a program simply requires moving the program code and then adjusting the code segment register to point to the base of the new code area.

Advantages of memory segmentation:

1. Segmentation provides a powerful memory management mechanism.
2. It allows programmers to partition their programs into modules that operate independently of one another.
3. Segments allow two processes to easily share data.
4. It allows to extend the address ability of a processor i.e. segmentation allows the use of 16 bit registers to give an addressing capability of 1 MB. Without segmentation, it would require 20 bit registers.
5. Segmentation makes it possible to separate the memory areas for stack, code and data.
6. It is possible to increase the memory size of code data or stack segments beyond 64 KB by allotting more than one segment for each area.

SEGMENT REGISTERS IN 8086

• Code segment register (CS): is used fro addressing memory location in the code segment of the memory, where the executable program is stored.
• Data segment register (DS): points to the data segment of the memory where the data is stored.
• Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in the memory.
• Stack Segment Register (SS): is used fro addressing stack segment of the memory. The stack segment is that segment of memory which is used to store stack data.

The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the 1MB memory locations. The four segment registers actually contain the upper 16 bits of the starting addresses of the four memory segments of 64 KB each with which the 8086 is working at that instant of time. A segment is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up of contiguous memory locations. It is independent, separately addressable unit. Starting address will always be changing. It will not be fixed.

8251 USART

8251 is a Universal Synchronous/Asynchronous Receiver/Transmitter packaged in a 28-pin DIP made by Intel. It is typically used for serial communication and was rated for 19.2 kilobits per second signalling rate.

Major Functions

8251 universal synchronous asynchronous receiver transmitter (USART) acts as a mediator between microprocessor and peripheral to transmit serial data into parallel form and vice versa.

1. It takes data serially from peripheral (outside devices) and converts into parallel data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it into serial form.
4. After converting data into serial form, it transmits it to outside device (peripheral).

ARCHITECTURE OF 8251

It contains the following blocks:

1. Data bus buffer –
   This block helps in interfacing the internal data bus of 8251 to the system data bus. The data transmission is possible between 8251 and CPU by the data bus buffer block.
2. Read/Write control logic –
   It is a control block for overall device. It controls the overall working by selecting the operation to be done. The operation selection depends upon input signal:
   
3. .Modem control (modulator/demodulator) –A device converts analog signals to digital signals and vice-versa and helps the computers to communicate over telephone lines or cable wires. The following are active-low pins of Modem.........................................................*DSR Data Set Ready signal is an input signal.*DTR: Data terminal Ready is an output signal.*CTS: It is an input signal which controls the data transmit circuit.*RTS: It is an output signal which is used to set the status RTS.
4. Transmit buffer –
   This block is used for parallel to serial converter that receives a parallel byte for conversion into serial signal and further transmission onto the common channel.
   • TXD: It is an output signal, if its value is one, means transmitter will transmit the data.
5. Transmit control –
   This block is used to control the data transmission with the help of following pins:
   • TXRDY: It means transmitter is ready to transmit data character.
   • TXEMPTY: An output signal which indicates that TXEMPTY pin has transmitted all the data characters and transmitter is empty now.
   • TXC: An active-low input pin which controls the data transmission rate of transmitted data.
6. Receive buffer –
   This block acts as a buffer for the received data.
   • RXD: An input signal which receives the data.
7. Receive control –
   This block controls the receiving data.
• RXRDY: An input signal indicates that it is ready to receive the data.
• RXC: An active-low output signal which controls the data transmission rate of received data.
• SYNDET/BD: An input or output terminal. External synchronous mode-input terminal and asynchronous mode-output terminal.

INTERFACING OF 8251 WITH 8086 

• The chip select for I/O mapped devices are generated by using a 3-to-8 decoder.

• The address lines A5, A6 and A7 are decoded to generate eight chip select signals 

(IOCS-0

to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 825lA.

• The address line A0 and the control signal M/IO(low) are used as enable for 

decoder.

• The line A1 of 8086 is connected to C/D(low) of 8251A to provide the internal 

addresses.

• The lines D0 – D7 connected to D0 – D7 of the processor to achieve parallel data 

transfer.

• The RESET and clock signals are supplied by 8284 clock generator. Here the 

processor 

clock is directly connected to 8251A. This clock controls the parallel data transf

er

between the processor and 825lA.

• 8251A in I/O mapped in the system is shown in the figure.

The peripheral clock (PCLK) supplied by 8284, is divided by suitable clock dividers 

like programmable timer 8254 and then used as clock for serial transmission and 

reception.

• In 8251A the transmission and reception baud rates can be different or same.

• The TTL logic levels of the serial data lines and the control signals necessary for 

serial transmission and reception are converted to RS232 logic levels using MAX232 

and then

terminated on a standard 9-pin D-.type connector.

• The device, which requires serial communication with processor, can be 

connected to this

9-pin D-type connector using 9-core cable.

MODES OF OPERATION

Control Words

There are two types of control word.

1. Mode instruction (setting of function)

2. Command (setting of operation)

1) Mode Instruction

Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait for write" at either internal reset or external reset. That is, the writing of a control word after resetting will be recognized as a "mode instruction."

Items set by mode instruction are as follows:

• Synchronous/asynchronous mode

• Stop bit length (asynchronous mode)

• Character length

• Parity bit

• Baud rate factor (asynchronous mode)

• Internal/external synchronization (synchronous mode)

• Number of synchronous characters (Synchronous mode)

The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of synchronous mode, it is necessary to write one-or two byte sync characters. If sync characters were written, a function will be set because the writing of sync characters constitutes part of mode instruction.

2) Command

Command is used for setting the operation of the 8251. It is possible to write a command whenever necessary after writing a mode instruction and sync characters.

Items to be set by command are as follows:

• Transmit Enable/Disable

• Receive Enable/Disable

• DTR, RTS Output of data.

• Resetting of error flag.

• Sending to break characters

• Internal resetting

• Hunt mode (synchronous mode)

Status Word

It is possible to see the internal status of the 8251 by reading a status word. The bit configuration of status word is shown in Fig. 5.

Pin Description

D 0 to D 7 (l/O terminal)

This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU.

RESET (Input terminal)

A "High" on this input forces the 8251 into "reset status." The device waits for the writing of "mode instruction." The min. reset width is six clock inputs during the operating status of CLK.

CLK (Input terminal)

CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC. However, the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at Asynchronous "x16" and "x64" mode.

WR (Input terminal)

This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the 8251.

RD (Input terminal)

This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.

C/D (Input terminal)

This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed.

CS (Input terminal)

This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses. Note: The device won’t be in "standby status"; only setting CS = High.

TXD (output terminal)

This is an output terminal for transmitting data from which serial-converted data is sent out. The device is in "mark status" (high level) after resetting or during a status when transmit is disabled. It is also possible to set the device in "break status" (low level) by a command.

TXRDY (output terminal)

This is an output terminal which indicates that the 8251is ready to accept a transmitted data character. But the terminal is always at low level if CTS = high or the device was set in "TX disable status" by a command. Note: TXRDY status word indicates that transmit data character is receivable, regardless of CTS or command. If the CPU writes a data character, TXRDY will be reset by the leading edge or WR signal.

TXEMPTY (Output terminal)

This is an output terminal which indicates that the 8251 has transmitted all the characters and had no data character. In "synchronous mode," the terminal is at high level, if transmit data characters are no longer remaining and sync characters are automatically transmitted. If the CPU writes a data character, TXEMPTY will be reset by the leading edge of WR signal. Note : As the transmitter is disabled by setting CTS "High" or command, data written before disable will be sent out. Then TXD and TXEMPTY will be "High". Even if a data is written after disable, that data is not sent out and TXE will be "High".After the transmitter is enabled, it sent out. (Refer to Timing Chart of Transmitter Control and Flag Timing)

TXC (Input terminal)

This is a clock input signal which determines the transfer speed of transmitted data. In "synchronous mode," the baud rate will be the same as the frequency of TXC. In "asynchronous mode", it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the serial data out of the 8251.

RXD (input terminal)

This is a terminal which receives serial data.

RXRDY (Output terminal)

This is a terminal which indicates that the 8251 contains a character that is ready to READ. If the CPU reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the CPU reads a data character before the next one is received completely, the preceding data will be lost. In such a case, an overrun error flag status word will be set.

RXC (Input terminal)

This is a clock input signal which determines the transfer speed of received data. In "synchronous mode," the baud rate is the same as the frequency of RXC. In "asynchronous mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.

SYNDET/BD (Input or output terminal)

This is a terminal whose function changes according to mode. In "internal synchronous mode." this terminal is at high level, if sync characters are received and synchronized. If a status word is read, the terminal will be reset. In "external synchronous mode, "this is an input terminal. A "High" on this input forces the 8251 to start receiving data characters.

In "asynchronous mode," this is an output terminal which generates "high level"output upon the detection of a "break" character if receiver data contains a "low-level" space between the stop bits of two continuous characters. The terminal will be reset, if RXD is at high level. After Reset is active, the terminal will be output at low level.

DSR (Input terminal)

This is an input port for MODEM interface. The input status of the terminal can be recognized by the CPU reading status words.

DTR (Output terminal)

This is an output port for MODEM interface. It is possible to set the status of DTR by a command.

CTS (Input terminal)

This is an input terminal for MODEM interface which is used for controlling a transmit circuit. The terminal controls data transmission if the device is set in "TX Enable" status by a command. Data is transmitable if the terminal is at low level.

RTS (Output terminal)

This is an output port for MODEM interface. It is possible to set the status RTS by a command.

ASSEMBLER DIRECTIVES OF 8086

Assembly languages are low-level languages for programming computers, microprocessors, microcontrollers, and other IC. They implement a symbolic representation of the numeric machine Codes and other constants needed to program a particular CPU architecture. This representation is usually defined by the hardware manufacturer, and is based on abbreviations that help the programmer to remember individual instructions, registers. An assembler directive is a statement to give direction to the assembler to perform task of the assembly process.

It control the organization if the program and provide necessary information to the assembler to understand the assembly language programs to generate necessary machine codes. They indicate how an operand or a section of the program is to be processed by the assembler.

An assembler supports directives to define data, to organise segments to control procedure, to define macros. It consists of two types of statements: instructions and directives. The instructions are translated to the machine code by the assembler whereas directives are not translated to the machine codes.

Assembler Directives of the 8086 Microprocessor

(a) The DB directive

(b) The DW directive

(c) The DD directive

(d) The STRUCT (or STRUC) and ENDS directives (counted as one)

(e)The EQU Directive

(f)The COMMENT directive

(g)ASSUME

(h) EXTERN

(i) GLOBAL

(j) SEGMENT

(k)OFFSET

(l) PROC

(m)GROUP

(n) INCLUDE

Data declaration directives:

1. DB – The DB directive is used to declare a BYTE -2-BYTE variable – A BYTE is made up of 8 bits.

Declaration examples:

Byte1 DB 10h

Byte2 DB 255 ; 0FFh, the max. possible for a BYTE

CRLF DB 0Dh, 0Ah, 24h ;Carriage Return, terminator BYTE

2. DW – The DW directive is used to declare a WORD type variable – A WORD occupies 16 bits or (2 BYTE).

Declaration examples:

Word DW 1234h

Word2 DW 65535; 0FFFFh, (the max. possible for a WORD)

3. DD – The DD directive is used to declare a DWORD – A DWORD double word is made up of 32 bits =2 Word’s or 4 BYTE.

Declaration examples:

Dword1 DW 12345678h

Dword2 DW 4294967295 ;0FFFFFFFFh.

4. STRUCT and ENDS directives to define a structure template for grouping data items.

(1) The STRUCT directive tells the assembler that a user defined uninitialized data structure follows. The uninitialized data structure consists of a combination of the three supported data types. DB, DW, and DD. The labels serve as zero-based offsets into the structure. The first element’s offset for any structure is 0. A structure element is referenced with the base “+” operator before the element’s name.

A Structure ends by using the ENDS directive meaning END of Structure.

Syntax:

STRUCT

Structure_element_name element_data_type?

. . .

. . .

. . .

ENDS

(OR)

STRUC

Structure_element_name element_data_type?

. . .

. . .

. . .

ENDS

DECLARATION:

STRUCT

Byte1 DB?

Byte2 DB?

Word1 DW?

Word2 DW?

Dword1DW?

Dword2 DW?

ENDS

Use OF STRUCT:

The STRUCT directive enables us to change the order of items in the structure when, we reform a file header and shuffle the data. Shuffle the data items in the file header and reformat the sequence of data declaration in the STRUCT and off you go. No change in the code we write that processes the file header is necessary unless you inserted an extra data element.

(5) The EQU Directive

The EQU directive is used to give name to some value or symbol. Each time the assembler finds the given names in the program, it will replace the name with the value or a symbol. The value can be in the range 0 through 65535 and it can be another Equate declared anywhere above or below.

The following operators can also be used to declare an Equate:

THIS BYTE

THIS WORD

THIS DWORD

A variable – declared with a DB, DW, or DD directive – has an address and has space reserved at that address for it in the .COM file. But an Equate does not have an address or space reserved for it in the .COM file.

Example:

A – Byte EQU THIS BYTE

DB 10

A_ word EQU THIS WORD

DW 1000

A_ dword EQU THIS DWORD

DD 4294967295

Buffer Size EQU 1024

Buffer DB 1024 DUP (0)

Buffed_ ptr EQU $ ; actually points to the next byte after the; 1024th byte in buffer.

(6) Extern:

It is used to tell the assembler that the name or label following the directive are I some other assembly module. For example: if you call a procedure which is in program module assembled at a different time from that which contains the CALL instructions ,you must tell the assembler that the procedure is external the assembler will put information in the object code file so that the linker can connect the two module together.

Example:

PROCEDURE -HERE SEGMENT

EXTERN SMART-DIVIDE: FAR ; found in the segment; PROCEDURES-HERE

PROCEDURES-HERE ENDS

(7) GLOBAL:

The GLOBAL directive can be used in place of PUBLIC directive .for a name defined in the current assembly module; the GLOBAL directive is used to make the symbol available to the other modules. Example:

GLOBAL DIVISOR:

WORD tells the assembler that DIVISOR is a variable of type of word which is in another assembly module or EXTERN.

(8) SEGMENT:

It is used to indicate the start of a logical segment. It is the name given to the the segment. Example: the code segment is used to indicate to the assembler the start of logical segment.

(9) PROC: (PROCEDURE)

It is used to identify the start of a procedure. It follows a name we give the procedure.

After the procedure the term NEAR and FAR is used to specify the procedure Example: SMART-DIVIDE PROC FAR identifies the start of procedure named SMART-DIVIDE and tells the assembler that the procedure is far.

(10) NAME:

It is used to give a specific name to each assembly module when program consists of several modules.

Example: PC-BOARD used to name an assembly module which contains the instructions for controlling a printed circuit board.

(11) INCLUDE:

It is used to tell the assembler to insert a block of source code from the named file into the current source module. This shortens the source module. An alternative is use of editor block command to cop the file into the current source module.

(12) OFFSET:

It is an operator which tells the assembler to determine the offset or displacement of a named data item from the start of the segment which contains it. It is used to load the offset of a variable into a register so that variable can be accessed with one of the addressed modes. Example: when the assembler read MOV BX.OFFSET PRICES, it will determine the offset of the prices.

(13) GROUP:

It can be used to tell the assembler to group the logical segments named after the directive into one logical group. This allows the contents of all he segments to be accessed from the same group. Example: SMALL-SYSTEM GROUP CODE, DATA, STACK-SEG.

Various addressing modes of 8086/8088

ADRESSING MODES OF 8086

The term addressing modes refers to the way in which the operand of an instruction is specified. Information contained in the instruction code is the value of the operand or the address of the result/operand. Following are the main addressing modes that are used on various platforms and architectures.

Various addressing modes of 8086/8088

1)      Register Addressing mode

2)      Immediate Addressing mode

3)      Register Indirect Addressing mode

4)      Direct Addressing mode

5)      Indexed Addressing mode

6)      Base Relative Addressing mode

7)      Base Indexed Addressing mode

Register addressing mode

It means that the register is the source of an operand for an instruction.

Data transfer using registers is called register addressing mode. Here operand value is present in register. For example

MOV AL,BL;

MOV AX,BX;

Immediate addressing mode

The addressing mode in which the data operand is a part of the instruction itself is known as immediate addressing mode.

When data is stored in code segment instead of data segment immediate addressing mode is used. Here operand value is present in the instruction. For example

MOV AX, 12345;

Register indirect addressing mode

This addressing mode allows data to be addressed at any memory location through an offset address held in any of the following registers: BP, BX, DI & SI.

Here operand offset is given in a cpu register. Register used are BX, SI(source index), DI(destination index),  or BP(base pointer). BP holds offset w.r.t Stack segment, but SI,DI and BX refer to data segment. For example

MOV [BX],AX;

ADD AX, [SI];

Direct addressing mode

The addressing mode in which the effective address of the memory location is written directly in the instruction.

When direct memory address is supplied as part of the instruction is called direct addressing mode. Operand offset value with respect to data segment is given in instruction. For example

MOV AX, [1234];

ADD AX, [1234];

Indexed addressing mode

In this addressing mode, the operands offset address is found by adding the contents of SI or DI register and 8-bit/16-bit displacements.

Here operand offset is given by a sum of a value held in either SI, or DI register and a constant displacement specified as an operand. For example

Lets take arrays as an example. This is very efficient way of accessing arrays.

My_array  DB ‘1’, ‘2’, ‘3’,’4,’5’;

MOV SI, 3;

MOV AL, My_array[3];

Based-index addressing mode

In this addressing mode, the offset address of the operand is computed by summing the base register to the contents of an Index register..

here operand offset is given by sum of either BX or BP with either SI or DI. For example

MOV AX, [BX+SI]

 JMP [BP+DI]

Based indexed with displacement mode

      Or

Base Relative Addressing mode

In this addressing mode, the operands offset is computed by adding the base register contents. An Index registers contents and 8 or 16-bit displacement
.

Operand offset given by a sum of a value held either in BP, or BX and a constant offset sepecified as an operand. For example

MOV AX,[BP+1];

JMP [BX+1];