INTERRUPTS IN 8086

DEFINITIONS:

1.Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices to access the microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor on how to handle the interrupt.

2.An interrupt is a condition that halts the microprocessor temporarily to work on a different task and then return to its previous task. Interrupt is an event or signal that request to attention of CPU. This halt allows peripheral devices to access the microprocessor.

THEORY:

Whenever an interrupt occurs the processor completes the execution of the current instruction and starts the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a program that tells the processor what to do when the interrupt occurs. After the execution of ISR, control returns back to the main routine where it was interrupted.

In 8086 microprocessor following tasks are performed when microprocessor encounters an interrupt:

1. The value of flag register is pushed into the stack. It means that first the value of SP (Stack Pointer) is decremented by 2 then the value of flag register is pushed to the memory address of stack segment.
2. The value of starting memory address of CS (Code Segment) is pushed into the stack.
3. The value of IP (Instruction Pointer) is pushed into the stack.
4. IP is loaded from word location (Interrupt type) * 04.
5. CS is loaded from the next word location.
6. Interrupt and Trap flag are reset to 0.

The different types of interrupts present in 8086 microprocessor are given by:

1. Hardware Interrupts –
   Hardware interrupts are those interrupts which are caused by any peripheral device by sending a signal through a specified pin to the microprocessor. There are two hardware interrupts in 8086 microprocessor. They are:
   • (A) NMI (Non Maskable Interrupt) – It is a single pin non maskable hardware interrupt which cannot be disabled. It is the highest priority interrupt in 8086 microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt. IP is loaded from word location 00008 H and CS is loaded from the word location 0000A H.
   • When this interrupt is activated, these actions take place −
     • Completes the current instruction that is in progress.
     • Pushes the Flag register values on to the stack.
     • Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack.
     • IP is loaded from the contents of the word location 00008H.
     • CS is loaded from the contents of the next word location 0000AH.
     • Interrupt flag and trap flag are reset to 0.
   • (B) INTR (Interrupt Request) – It provides a single interrupt request and is activated by I/O port. This interrupt can be masked or delayed. It is a level triggered interrupt. It can receive any interrupt type, so the value of IP and CS will change on the interrupt type received.
   • These actions are taken by the microprocessor −
     • First completes the current instruction.
     • Activates INTA output and receives the interrupt type, say X.
     • Flag register value, CS value of the return address and IP value of the return address are pushed on to the stack.
     • IP value is loaded from the contents of word location X × 4
     • CS is loaded from the contents of the next word location.
     • Interrupt flag and trap flag is reset to 0
2. Software Interrupts -

Some instructions are inserted at the desired position into the program to create interrupts. These interrupt instructions can be used to test the working of various interrupt handlers. It includes −

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt type number. There are 256 interrupt types under this group.

Its execution includes the following steps −

• Flag register value is pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of the word location ‘type number’ × 4
• CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0

The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. −

• TYPE 0 interrupt represents division by zero situation.
• TYPE 1 interrupt represents single-step execution during the debugging of a program.
• TYPE 2 interrupt represents non-maskable NMI interrupt.
• TYPE 3 interrupt represents break-point interrupt.
• TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and interrupts from 32 to Type 255 are available for hardware and software interrupts.

INT 3-Break Point Interrupt Instruction

It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program so that when the processor reaches there, then it stops the normal execution of program and follows the break-point procedure.

Its execution includes the following steps −

• Flag register value is pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of the word location 3×4 = 0000CH
• CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0

INTO - Interrupt on overflow instruction

It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow flag is set to 1 and branches to the interrupt handler whose interrupt type number is 4. If the overflow flag is reset then, the execution continues to the next instruction.

Its execution includes the following steps −

• Flag register values are pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of word location 4×4 = 00010H
• CS is loaded from the contents of the next word location.
• Interrupt flag and Trap flag are reset to 0